सीपीयू शिल्पों की तुलना

मुक्त ज्ञानकोश विकिपीडिया से

कम्प्यूटर शिल्प (Computer architecture) को प्रायः 8, 16, 32, or 64 बिट आदि के द्वारा समझा जाता है। किन्तु कम्प्यूटर शिल्प में इसके अलावा भी कुछ अन्य डेटा-साइज होते हैं।

शिल्प (Architectures)[संपादित करें]

नीचे की सारणी में सीपीयू शिल्प से सम्बन्धित मूलभूत सूचनाओं की ही तुलना की गैइ है।

शिल्प बिट संख्या संस्करण कब आया Max # Operands टाइप डिजाइन रजिस्टर इंस्ट्रक्शन इन्कोडिंग ब्रांच इवैलुएशन Endianness Extensions मुक्त रॉयल्टी-मुक्त
Alpha 64 1992 3 Register-Register RISC 32 Fixed Condition register Bi MVI, BWX, FIX, CIX नहीं Unknown
ARM 32 ARMv7 and earlier 1983 3 Register-Register RISC 16 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit) Condition code Bi NEON, Jazelle, VFP, TrustZone, LPAE Unknown नहीं
ARM 64 ARMv8[1] 2011[2] 3 Register-Register RISC 30 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit), A64 Condition code Bi NEON, Jazelle, VFP, TrustZone Unknown नहीं
AVR32 32 Rev 2 2006 2-3 RISC 15 Variable[3] Big Java Virtual Machine Unknown Unknown
Blackfin 32 2000 RISC[4] 8 Little[5] Unknown Unknown
DLX 32 1990 3 RISC 32 Fixed (32-bit) Big Unknown Unknown
eSi-RISC 16/32 2009 3 Register-Register RISC 8-72 Variable(16 or 32-bit) Compare and branch and condition register Bi User-defined instructions नहीं नहीं
Itanium (IA-64) 64 2001 Register-Register EPIC 128 Condition register Bi (selectable) Intel Virtualization Technology हाँ हाँ
M32R 32 1997 RISC 16 Fixed (16- or 32-bit) Bi Unknown Unknown
m68k 16/32 1979 CISC 16 Big Unknown Unknown
Mico32 32 2006 3 Register-Register RISC 32[6] Fixed (32-bit) Compare and branch Big User-defined instructions हाँ[7] हाँ
MIPS 64 (32→64) 5 1981 3 Register-Register RISC 32 Fixed (32-bit) Condition register Bi MDMX, MIPS-3D Unknown नहीं
MMIX 64 1999 3 Register-Register RISC 256 Fixed (32-bit) Big हाँ हाँ
PA-RISC (HP/PA) 64 (32→64) 2.0 1986 3 RISC 32 Fixed Compare and branch Big Multimedia Acceleration eXtensions (MAX), MAX-2 नहीं Unknown
PowerPC 32/64 (32→64) 2.06[8] 1991 3 Register-Register RISC 32 Fixed, Variable Condition code Big/Bi AltiVec, APU, VSX, Cell हाँ[9] नहीं
S+core 16/32 2005 RISC Little Unknown Unknown
Series 32000 32 1982 5 Memory-Memory CISC 8 Variable Huffman coded, up to 23 bytes long Condition Code Little BitBlt instructions Unknown Unknown
SPARC 64 (32→64) V9 1985 3 Register-Register RISC 31 (of at least 55) Fixed Condition code Big → Bi VIS 1.0, 2.0, 3.0 हाँ हाँ[10]
SuperH (SH) 32 1990s 2 Register-Register/ Register-Memory RISC 16 Fixed Condition Code (Single Bit) Bi Unknown Unknown
System/360 / System/370 / z/Architecture 64 (32→64) 3 1964 Register-Memory/Memory-Memory CISC 16 Fixed Condition code Big Unknown Unknown
VAX 32 1977 6 Memory-Memory CISC 16 Variable Compare and branch Little VAX Vector Architecture Unknown Unknown
x86 32 (16→32) 1978 2 Register-Memory CISC 8 Variable Condition code Little MMX, 3DNow!, SSE, PAE, नहीं नहीं
x86-64 64 2003 2 Register-Memory CISC 16 Variable Condition code Little MMX, 3DNow!, PAE, AVX नहीं नहीं

सूक्ष्मशिल्प (Microarchitectures)[संपादित करें]

नीचे की सारणी में प्रमुख सूक्ष्मशिल्पों की तुलना की गई है।

Microarchitecture Pipeline stages Misc
AMD K5 Out-of-order execution, register renaming, speculative execution
AMD K6 Superscalar, branch prediction
AMD K6-III Branch prediction, speculative execution, out-of-order execution[11]
AMD K7 Out-of-order execution, branch prediction, Harvard architecture
AMD K8 64-bit, integrated memory controller, 16 byte instruction prefetching
AMD K10 Superscalar, out-of-order execution, 32-way set associative L3 victim cache, 32-byte instruction prefetching
ARM7TDMI(-S) 3
ARM7EJ-S 5
ARM810 5
ARM9TDMI 5
ARM1020E 6
XScale PXA210/PXA250 7
ARM1136J(F)-S 8
ARM1156T2(F)-S 9
ARM Cortex-A5 8
ARM Cortex-A8 13
ARM Cortex-A9 Out-of-order, speculative issue, superscalar
ARM Cortex-A15 Multicore (up to 16)
AVR32 AP7 7
AVR32 UC3 3 Harvard architecture
Bobcat Out-of-order execution
Bulldozer Shared L3 cache, multithreading, multicore, integrated memory controller
Crusoe In-order execution, 128-bit VLIW, integrated memory controller
Efficeon In-order execution, 256-bit VLIW, fully integrated memory controller
Cyrix Cx5x86 6[12] Branch prediction
Cyrix 6x86 Superscalar, superpipelined, register renaming, speculative execution, out-of-order execution
DLX 5
eSi-3200 5 In-order, speculative issue
eSi-3250 5 In-order, speculative issue
EV4 (Alpha 21064) Superscalar
EV7 (Alpha 21364) Superscalar design with out-of-order execution, branch prediction, 4-way SMT, integrated memory controller
EV8 (Alpha 21464) Superscalar design with out-of-order execution
P5 (Pentium) 5 Superscalar
P6 (Pentium Pro) 14 Speculative execution, Register renaming, superscalar design with out-of-order execution
P6 (Pentium II) Branch prediction
P6 (Pentium III) 10
Itanium 8[13] Speculative execution, branch prediction, register renaming, 30 execution units, multithreading
NetBurst (Willamette) 20 Simultaneous multithreading
NetBurst (Northwood) 20 Simultaneous multithreading
NetBurst (Prescott) 31 Simultaneous multithreading
NetBurst (Cedar Mill) 31 Simultaneous multithreading
Core 14
Intel Atom 16 Simultaneous multithreading, in-order. No instruction reordering, speculative execution, or register renaming.
Nehalem Simultaneous multithreading, integrated memory controller, L1/L2/L3 cache
Sandy Bridge Simultaneous multithreading, multicore, integrated memory controller, L1/L2/L3 cache. 2 threads per core.
Haswell 14 Multicore
LatticeMico32 6 Harvard architecture
POWER1 Superscalar, out-of-order execution
POWER3 Superscalar, out-of-order execution
POWER4 Superscalar, speculative execution, out-of-order execution
POWER5 Simultaneous multithreading, out-of-order execution, integrated memory controller
POWER6 2-way simultaneous multithreading, in-order execution
POWER7 4 SMT threads per core, 12 execution units per core
PowerPC 401 3
PowerPC 405 5
PowerPC 440 7
PowerPC 470 9 SMP
PowerPC A2 15
PowerPC e300 4 Superscalar, Branch prediction
PowerPC e500 Dual 7 stage Multicore
PowerPC e600 3-issue 7 stage Superscalar out-of-order execution, branch prediction
PowerPC e5500 4-issue 7 stage Out-of-order, multicore
PowerPC 603 4 5 execution units, branch prediction. No SMP.
PowerPC 603q 5 In-order
PowerPC 604 6 Superscalar, out-of-order execution, 6 execution units. SMP support.
PowerPC 620 5 Out-of-order execution- SMP support.
PWRficient Superscalar, out-of-order execution, 6 execution units
R4000 8 Scalar
StrongARM SA-110 5 Scalar, in-order
SuperH SH2 5
SuperH SH2A 5 Superscalar, Harvard architecture
SPARC Superscalar
HyperSPARC Superscalar
SuperSPARC Superscalar, in-order
SPARC64 VI/VII/VII+ Superscalar, out-of-order[14]
UltraSPARC 9
UltraSPARC T1 6 Open source, multithreading, multi-core, 4 threads per core, integrated memory controller
UltraSPARC T2 8 Open source, multithreading, multi-core, 8 threads per core
SPARC T3 8 Multithreading, multi-core, 8 threads per core, SMP
SPARC T4 16 Multithreading, multi-core, 8 threads per core, SMP, out-of-order
VIA C7 In-order execution
VIA Nano (Isaiah) Superscalar out-of-order execution, branch prediction, 7 execution units
WinChip 4 In-order execution

इन्हें भी देखें[संपादित करें]

सन्दर्भ[संपादित करें]

  1. ↑ "ARMv8 Technology Preview" (PDF). मूल (PDF) से 10 जून 2018 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
  2. ↑ "ARM goes 64-bit with new ARMv8 chip architecture". मूल से 3 मार्च 2012 को पुरालेखित. अभिगमन तिथि 26 मई 2012.
  3. ↑ "AVR32 Architecture Document" (PDF). Atmel. मूल (PDF) से 18 मार्च 2012 को पुरालेखित. अभिगमन तिथि 2008-06-15.
  4. ↑ "Blackfin Processor Architecture Overview". Analog Devices. मूल से 22 मई 2009 को पुरालेखित. अभिगमन तिथि 2009-05-10.
  5. ↑ "Blackfin memory architecture". Analog Devices. मूल से 16 जून 2011 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  6. ↑ "LatticeMico32 Architecture". Lattice Semiconductor. मूल से 23 जून 2010 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  7. ↑ "Open Source Licensing". Lattice Semiconductor. मूल से 20 जून 2010 को पुरालेखित. अभिगमन तिथि 2009-12-18.
  8. ↑ "Power ISA V2.06" (PDF). IBM. अभिगमन तिथि 2009-07-04.[मृत कड़ियाँ]
  9. ↑ http://www.ibm.com/developerworks/power/newto/#2 Archived 2012-08-29 at the वेबैक मशीन New to Cell/B.E., multicore, and Power Architecture technology
  10. ↑ http://www.sparc.org/specificationsDocuments.html# Archived 2012-02-22 at the वेबैक मशीन#ArchLic SPARC Architecture License
  11. ↑ http://www.amd.com/us-en/Processors/ProductInformation/0, 30_118_1260_1288%5E1295,00.html
  12. ↑ "संग्रहीत प्रति". मूल से 4 मई 2012 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
  13. ↑ Intel Itanium 2 Processor Hardware Developer's Manual. p. 14. <http://www.intel.com/design/itanium2/manuals/25110901.pdf Archived 2006-12-12 at the वेबैक मशीन> (2002) [Retrieved November 28, 2011]
  14. ↑ "संग्रहीत प्रति". मूल से 22 सितंबर 2012 को पुरालेखित. अभिगमन तिथि 21 सितंबर 2012.
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